A semiconductor chip is obtained by dicing an oblong or square chip 101 formed on a substantially disk-shaped silicon wafer. For this reason, chips on a wafer are often arranged orderly in a lattice pattern, as shown in FIG. 1. In addition, a wafer effective area 102, where a predetermined sensitizer film thickness is ensured, is set to maintain a predetermined distance from the outer edge of a wafer 100. If a chip is not wholly placed in the range of the wafer effective area 102, the chip 101 can be defective even when it is wholly present inside the wafer 100. Even when a dicing line (103) called an orientation flat is present, a predetermined distance is set between the wafer effective area 102 and the edge formed by the orientation flat 103.
An exposure apparatus prints a pattern such that a plurality of chips are arranged in a lattice pattern in the wafer effective area 102. When the relative positional relationship between the lattice-like chip arrangement (also called a chip lattice) and the wafer effective area changes, the number of chips available from one wafer varies. Hence, it is demanded to obtain, from the relationship between the wafer effective area and the chip shape (size), a relative positional relationship between the chip lattice and the wafer effective area to acquire chips as many as possible.
As prior arts related to the wafer position determination method, Japanese Patent Laid-Open Nos. 07-211622 (to be referred to as patent reference 1 hereinafter), 2000-195824 (to be referred to as patent reference 2 hereinafter), and 2003-257843 (to be referred to as patent reference 3 hereinafter) are proposed.
The wafer position determination method disclosed in patent reference 1 is a four-point comparison method (to be referred to as a method A hereinafter) in which a position where the number of available chips is maximized is selected for four cases wherein one of the chip center, corner, and the median of each side is set at the wafer center. The wafer position determination method disclosed in patent reference 2 is a multiple-point comparison method (to be referred to as a method B hereinafter) in which the number of available chips is counted while setting, at the wafer center, a plurality of points set in the chip plane, and a position where the number of available chips is maximized is selected as the wafer center. In both patent references 1 and 2, the point at which the number of available chips is maximized is selected as the wafer center from a plurality of set points. These methods cannot always guarantee an optimum solution. Patent reference 3 discloses a method capable of reliably presenting the relative position between the wafer and the chip lattice which maximize the number of available chips (the method disclosed in patent reference 3 will be referred to as a method C hereinafter).
However, the method disclosed in patent reference 3 presents a relative position when the chip set available on the wafer is in contact with the boundary of the wafer effective area at two or more points. For this reason, although the number of available chips is correct, if the relative position slightly shifts from the presented relative position, chips can be off the wafer effective area and become ineffective.
In this case, a plurality of relative positions where the number of available chips is maximized are set as the area boundary of relative positions where a set with the maximum number of chips is available, and the center of gravity (e.g., the center of gravity of the position of a wafer representative point corresponding to the relative position when the chip lattice is fixed) of these relative positions is set as the wafer position (wafer representative point position). However, if there are a plurality of sets which include chips in equal and maximum number in different chip set shapes, the number of available chips when the center of gravity is set as the wafer position is not always maximum even when the center of gravity of relative positions (wafer representative points) corresponding to the sets are obtained.